A chip can look finished in a diagram and still fail at the one place that matters: the clock. A calculation that works in principle may take too long once it is turned into hardware and laid out across a real device. Fixing that means more than writing code. Designers must test, inspect timing reports, change the hardware blueprint, and try again.
A May 2026 arXiv paper describes a system built to run that whole loop. The authors say their multi-agent system, Design Conductor 2.0, spent about 80 hours designing an accelerator for language-model inference. Its task was to turn a research idea for compressing memory into a hardware design, verify the design in simulation, and map it to an FPGA. The intriguing part is not that it produced code. It is that it used feedback from engineering tools to revise the design.
The accelerator, named VerTQ, targets a memory burden that grows as a language model handles longer conversations. During text generation, a model keeps a cache of information about earlier tokens so it can use that context when choosing what comes next. The cache is useful, but it can consume substantial memory and bandwidth. TurboQuant, the method VerTQ was designed to implement, aims to shrink that cache. VerTQ’s proposed hardware also performs attention calculations while the cache remains compressed, rather than repeatedly expanding it first.
The researchers gave the system a broad assignment and a collection of constraints: use a specified FPGA, aim for a 125 MHz internal clock, connect the design to the vLLM inference framework, and test it against a software implementation of TurboQuant. They also supplied reference material and an existing implementation. From there, the paper reports, the system handled architecture exploration, hardware description, verification, synthesis, placement and routing, and system simulation.
That sequence matters because chip design is a negotiation between what a circuit should do and what its physical layout can manage. A design may be logically correct but miss its timing target because signals must travel too far or too much work is crammed into one clock cycle. Design Conductor’s newer approach, as its authors describe it, was to take high-level feedback from timing and placement tools, reason about the results, and make substantial changes to the hardware description. When the team changed the timing target after an initial design, the system reworked large parts of the circuit.
One telling obstacle involved a mathematical operation inside the attention pipeline. The system built a specialized unit for calculating negative exponentials, a step used in softmax, which helps determine how strongly different pieces of context influence an output. A polynomial approximation in the first version produced too much error in some cases. The system found the problem and replaced it with a fifth-order Taylor polynomial evaluated using a method called Horner’s algorithm. In plain terms, it changed how the approximation was organized so the hardware could calculate it with acceptable accuracy and speed.
That fix illustrates both the attraction and the risk of this approach. The paper says the system compared results with a Python reference and investigated numerical differences, but its hardware deliberately used lower-precision arithmetic in some places to save resources. Some deviations were expected trade-offs; others might have signaled a bug. The design team had to treat discrepancies as clues to investigate, not automatically dismiss them as harmless.
The reported design is substantial: an eight-way attention decoder with 5,129 mixed-precision FP16 and FP32 arithmetic units. The authors report mapping it to a Xilinx XCVU29P-3 FPGA design at 125 MHz. They also estimate that an eight-way version would occupy about 5.7 mm2 in a 16 nm process. That area is an estimate, not a measurement from a manufactured chip. The FPGA result and the projected silicon area are different kinds of evidence.
There is another important boundary. The system was integrated with a simulation of Qwen3-4B, but limited computing resources restricted the test to all 36 model layers at a context size of 64. The authors note that larger tests, such as a context size of 32k, would require more simulation capacity. So the paper does not show VerTQ running as a finished accelerator in a deployed device, nor does it establish performance across long real-world workloads.
The paper describes three other designs as well, including a floating-point adder tested with 918,000 vectors. Those projects suggest the system was being tried on more than one kind of hardware task. Still, this is the authors’ account of their own system, not an independent comparison proving that it outperforms human engineering teams. The paper also acknowledges practical weaknesses: the system can spend too long checking simple questions, sometimes pursues overly ambitious clock targets, and may propose complex hardware changes when a simpler tool-setting adjustment would do.
Most revealing is the authors’ admission that human review remains the bottleneck. People still need to set meaningful constraints, scrutinize what the system builds, and decide whether a design is safe and useful enough to take further. The new approach is not to remove engineers from chip design; it is to let an automated team keep working through the slow cycle of proposing, testing, and revising.
That shift may be the real result. A conversational AI can sketch a circuit, but useful hardware demands sustained attention to details that only appear after simulation and physical-design tools weigh in. Design Conductor’s reported achievement is an early demonstration of a system that can stay in that loop. Whether it can do so reliably at the scale of commercial silicon remains an open engineering question—and one that the next round of tests will have to answer.
