Imagine three robots sent into a cluttered warehouse. They must divide up ten destinations, choose an order for each robot’s stops, then find paths around obstacles. That sounds like one planning problem. To the hardware, it is three different puzzles—and a small experimental chip turns out to be useful for some, awkward for another.
The device, examined in an arXiv paper posted August 7, 2026, is a CMOS Ising chip. It is not a quantum computer. Its 45 “spins” are variables that can each take one of two states, and their interactions encode a puzzle whose low-energy arrangements correspond to candidate solutions. The chip’s compactness is appealing for robots with limited power. But its small spin budget and narrow range of allowed interaction strengths impose a question more practical than whether a problem can be written in Ising form: can it be made to fit this particular chip?
The researchers tested three stages of robot planning: sharing targets among robots, ordering targets into tours, and finding paths through a map. They did not ask the chip to take over the whole planner. Instead, classical software broke large problems into smaller pieces, sent those pieces to the chip where possible, then checked and assembled the returned candidates. The first clue was that each stage ran into a different hardware limit.
Pathfinding seemed like a dead end at full scale. Even a modest 10 × 10 grid needs 100 variables in the paper’s most compact full-map model—more than twice the chip’s capacity. So the team shrank the question. At each step, the planner considered a 5 × 5 patch around the robot, asked the chip to suggest a short local route, and then moved the patch forward. The software discarded disconnected or looping answers rather than trusting every low-energy result.
That patchwork approach was tested on 1,000 randomly generated single-destination queries in 10 × 10 grids with 20% obstacle density. The chip-assisted planner found valid routes in 996 cases. Its median path length was 6.0, matching the medians reported for breadth-first search, A*, and greedy best-first search. The energy comparison favored the chip: 14 μJ per query, versus 523 μJ for A*. But the route took a median 1.6 ms in accumulated chip-solving time, while A* finished in 35 μs on the CPU. The first answer to the puzzle: the chip could find useful local paths, but it did not make planning faster.
Target sharing produced a more striking clue. The researchers repeatedly split groups of robots and destinations, using distance-weighted partitions to guide which nodes belonged together. On 100 randomly generated cases with three robots and ten targets, the Ising method’s median total route cost was 29, close to 28 for the strongest classical assignment baseline. Its median energy figure was 9 μJ, compared with 73 mJ for that baseline—roughly 8,000 times lower under the paper’s accounting.
Why would this puzzle suit the chip better? Each split can be expressed as a binary partition, and the chip’s returned states directly suggest candidate groupings. The planner can repeat the split until the robots are separated, then handle leftover target bundles in software. Here, the small device’s natural operation lines up with the shape of the task. The researchers also tried several ways of translating the mathematical puzzle into the chip’s limited numerical range; no single translation always won, so they tested a portfolio of alternatives.
The tour-ordering stage revealed the catch. To decide which stop comes first, second, and third, a standard formulation needs variables that encode a valid permutation. Those rules must be enforced with strong penalties. The chip’s allowed interaction strengths run only from −7 to +7, too narrow to reliably enforce those constraints. Even a seven-target tour slightly exceeds the 45-spin limit, and fitting the number of variables alone would not solve the coefficient problem.
The researchers devised a clever workaround: split targets into clusters, solve smaller ordering problems, and use branching to bring slightly oversized subproblems within the spin budget. But the tour results were evaluated with a logical Ising solver, not the physical CMOS chip. On that backend, the method achieved a median optimality gap of 0.0% on 100 ten-target instances. That is an interesting result about the method—not a demonstration that this chip can yet perform that stage.
Put the pieces together and the whole pipeline comes within a median 9.1% of the strong classical planner’s route cost: 32.0 versus 28.0. The paper reports median energy of 3.07 mJ, compared with 399 mJ for the strong baseline, or about 130 times lower. But the Ising pipeline took 341 ms, while the strong classical pipeline took 27 ms and a faster classical one took 0.99 ms. Thousands of small pathfinding calls dominated the Ising pipeline’s delay.
There is another reason to read the energy ratios carefully. The chip’s energy figures count accelerator energy, while the classical figures use a CPU energy estimate based on a per-core power assumption. Host-side work—decomposing problems, mapping them to the hardware, checking answers, and stitching routes together—is not included in the reported accelerator energy. And the tour stage’s end-to-end chip cost is projected from logical solver calls, not measured on the physical chip. Those choices do not erase the results, but they mean the headline ratios are not full-system, like-for-like energy measurements.
So where does the chip fit? Not as a tiny robotic brain replacing a conventional planner. The evidence points to a narrower role: a low-power candidate generator for particular subproblems, when software can reshape the problem to fit the hardware and verify what comes back. Target sharing looks like a natural match; local pathfinding can work but costs time; tour ordering still exceeds the chip’s numerical comfort zone. The puzzle’s answer is not that the Ising machine can plan everything. It is that knowing which part of the plan to give it may matter more than making the chip solve a bigger puzzle.
